Field of the Invention
Generally, the present disclosure relates to sophisticated semiconductor devices, and, more specifically, to semiconductor devices with improved gate connections on isolation structures.
Description of the Related Art
In an effort to maintain Moore's Law as a self-fulfilling prophecy, the semiconductor industry in recent years has sought to reduce the sizes of semiconductor devices. Efforts to do so have led to the development of FinFET devices, in which a gate electrode is disposed on the tops and sides of a fin providing the gate channel. Sources and drains may be formed in or on the fin in proximity to the gate.
Gate electrodes, sources, and drains require contacts, frequently comprising metal, to allow signals to travel to and from the gate, source, and drain on the one hand and other components of the semiconductor device on the other. However, if contacts to sources and/or drains are relatively close to gate electrodes, which is essentially required to reduce FinFET device dimensions, and the contacts and gate electrodes are insufficiently electrically isolated, parasitic capacitance may arise, which degrades device performance. In many cases, parasitic capacitance may contribute to an increase in the overall effective capacitance of one or more circuit formed from the finFET devices, which may degrade performance of a semiconductor chip containing the finFET devices.
Accordingly, it would be desirable to have a semiconductor device with low parasitic capacitance and high performance.